Computer hard disk drives, also known as fixed disk drives or hard disk drives, have become a de facto data storage standard for computer systems. Their proliferation can be directly attributed to their low cost, high storage capacity and reliability, in addition to wide availability, low power consumption, fast data transfer speeds and decreasing physical size.
Disk drives typically include one or more rotating magnetic platters encased within an environmentally controlled housing. The hard drive may have several read/write heads that interface with the magnetic platters. The disk drive may further include electronics for reading and writing data and for interfacing with other devices. The electronics are coupled with the read/write heads and include circuits to control head positioning and to generate or sense electromagnetic fields on the platters. The electronics encode data received from a host device, such as a personal computer, and translate the data into magnetic encodings, which are written onto the platters. When data is requested, the electronics locate the data, sense the magnetic encodings, and translate the encodings into binary digital information. Error checking and correction may also be applied to ensure accurate storage and retrieval of data.
The read/write heads detect and record the encoded data as areas of magnetic flux. The data are encoded by the presence or absence of a flux reversal between two contiguous areas of the platter. Data may be read using a method known as xe2x80x9cPeak Detectionxe2x80x9d by which a voltage peak imparted in the read/write head is detected when a flux reversal passes the read/write head. However, increasing storage densities, requiring reduced peak amplitudes, better signal discrimination and higher platter rotational speeds are pushing the peaks in closer proximity. Thus, peak detection methods are becoming increasingly complex.
Advancements in read/write heads and in the methods of interpreting magnetic encodings have been made. For example, magneto-resistive (xe2x80x9cMRxe2x80x9d) read/write heads have been designed with increased sensitivity and increased signal discrimination. In addition, technology known as Partial Response Maximum Likelihood (xe2x80x9cPRMLxe2x80x9d) has been developed. PRML disk drives function based an algorithm implemented in the disk drive electronics to read analog waveforms generated by the magnetic flux reversals. Instead of looking for peak values, PRML based drives digitally sample the analog waveform (the xe2x80x9cPartial Responsexe2x80x9d) and carry out advanced signal processing techniques to determine a most-likely bit pattern represented by the wave form (the xe2x80x9cMaximum Likelihoodxe2x80x9d). PRML technology tolerates more noise in the magnetic signals, permitting use of lower quality platters and read/write heads, which also increases manufacturing yields and lowers costs.
With hard drives typically differentiated by factors such as cost/unit of storage, data transfer rate, power requirement, and form factor (physical dimensions), there is a need for enhanced hard drive components which prove cost effective in optimizing storage capacity, operating speed, reliability and power efficiency. An example of an area includes PRML electronics used to calibrate and tune the PRML read/write channel. These electronics may include a view DAC circuit used to determine a performance level of the operation of the PRML based read/write channel. The view DAC provides an analog output signal converted from an internal clock signal and data at an internal 7-bit digital port. The analog signal is used in conjunction with external hardware and software devices to determine the level of operation for the PRML electronics. When the PRML read/write channel is operating at a level that is less than optimal, the external hardware and software devices are used to tune the circuit to an optimal level using information provided with the view DAC output signal. Several component of the PRML read/write channel are calibrated during the tuning operation. The tuning/calibration operation may be time-consuming, labor-intensive and thereby add to the cost of the PRML read/write channel.
Accordingly, there is a need in the art for a View DAC Feedback inside of an analog front for a PRML read/write channel.
A view DAC feedback inside of an analog front circuit for a partial response, maximum likelihood (xe2x80x9cPRMLxe2x80x9d) read/write channel is disclosed. The view DAC circuit derives an analog signal associated with a performance level for various electronic components of the PRML based read write channel. The analog signal is derived from a 7-bit digital port and a clock signal. The analog signal may be provided to external hardware and used for diagnostic purposes.
An embodiment for a view DAC feedback includes a PRML based read/write channel having a read circuit including an analog front circuit, a view DAC circuit, and a view DAC feedback circuit. The analog front circuit may include multiple electronic components configured to process analog information that is received from a magnetic data storage medium. The analog information may be converted to a digital signal and further processed by a digital circuit configured to carry out digital signal processing techniques.
The view DAC circuit may be configured to convert digital signals to an analog signal associated with the digital signals. The analog signal is provided at a view DAC output node. The view DAC circuit has an input coupled with an internal PRML digital port having high-speed digital signals and a clock input coupled with an internal clock generator. In an embodiment, an auxiliary multiplexer is coupled with the clock input and configured to selectively couple one of multiple internal clock generators with the view DAC circuit.
The view DAC feedback circuit is coupled with the view DAC output node. The view DAC feedback is configured to selectively couple the view DAC output to the analog front circuit during a calibration procedure. The analog signal provided at the view DAC output may be used for diagnostics for the performance of the PRML read/write channel. In an embodiment, the view DAC feedback circuit couples the view DAC output with the analog front circuit to optimize performance for the PRML read/write channel.
An embodiment of a method of tuning a read circuit of a PRML based read/write channel, the method comprising the acts of: generating an analog signal associated with a performance level of the PRML based read channel, the analog signal being generated from digital information from an internal digital bus; and selectively coupling the analog signal to an analog front circuit for a read component of the PRML read/write channel. The view DAC feed back provides a circuit that uses existing PRML analog front circuit to calibrate the PRML read/write channel.
In an embodiment, the act of generating an analog signal may further include selecting a digital clock signal from a servo clock signal and a read/write clock signal. The selected digital clock signal and a 7-bit digital data signal received from an internal digital port for the PRML read/write channel are converted to the analog associated with a performance level of the PRML based read/write channel. The analog signal is provided to the analog front circuit, optimizing performance of components of the PRML based read/write channel.
The foregoing discussion of the summary of the invention is provided only by way of introduction. Nothing in this section should be taken as a limitation on the claims, which define the scope of the invention. Additional objects and advantages of the present invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the claims.